=============================================================================== MPTable, version 2.0.12 ------------------------------------------------------------------------------- MP Floating Pointer Structure: location: BIOS physical address: 0x000ff780 signature: '_MP_' length: 16 bytes version: 1.4 checksum: 0x63 mode: Virtual Wire ------------------------------------------------------------------------------- MP Config Table Header: physical address: 0x000fce60 signature: 'PCMP' base table length: 416 version: 1.4 checksum: 0x30 OEM ID: 'AMD ' Product ID: 'RS780 ' OEM table pointer: 0x00000000 OEM table size: 0 entry count: 39 local APIC address: 0xfee00000 extended table length: 124 extended table checksum: 188 ------------------------------------------------------------------------------- MP Config Base Table Entries: -- Processors: APIC ID Version State Family Model Step Flags 0 0x10 BSP, usable 15 10 0 0x178bfbff 1 0x10 AP, usable 15 10 0 0x178bfbff 2 0x10 AP, usable 15 10 0 0x178bfbff 3 0x10 AP, usable 15 10 0 0x178bfbff 4 0x10 AP, usable 15 10 0 0x178bfbff -- Bus: Bus ID Type 0 PCI 1 PCI 2 PCI 3 PCI 4 ISA -- I/O APICs: APIC ID Version State Address 5 0x21 usable 0xfec00000 -- I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID INT# ExtINT conforms conforms 4 0 5 0 INT conforms conforms 4 1 5 1 INT conforms conforms 4 0 5 2 INT conforms conforms 4 3 5 3 INT conforms conforms 4 4 5 4 INT conforms conforms 4 5 5 5 INT conforms conforms 4 6 5 6 INT active-hi edge 4 8 5 8 INT conforms conforms 4 9 5 9 INT conforms conforms 4 12 5 12 INT conforms conforms 4 13 5 13 INT conforms conforms 4 14 5 14 INT conforms conforms 4 15 5 15 INT active-lo level 0 20:A 5 16 INT active-lo level 0 20:C 5 18 INT active-lo level 0 18:A 5 16 INT active-lo level 0 18:B 5 17 INT active-lo level 0 19:A 5 18 INT active-lo level 0 19:B 5 19 INT active-lo level 0 17:A 5 22 INT active-lo level 0 2:A 5 18 INT active-lo level 1 0:A 5 18 INT active-lo level 0 5:A 5 17 INT active-lo level 2 0:A 5 17 INT active-lo level 0 6:A 5 18 INT active-lo level 3 6:A 5 21 -- Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID INT# ExtINT conforms conforms 0 0:A 255 0 NMI conforms conforms 0 0:A 255 1 ------------------------------------------------------------------------------- MP Config Extended Table Entries: -- bus ID: 0 address type: I/O address address base: 0x7000 address range: 0x8000 -- bus ID: 0 address type: I/O address address base: 0x0 address range: 0x100 -- bus ID: 0 address type: memory address address base: 0xa0000 address range: 0x20000 -- bus ID: 0 address type: memory address address base: 0xfe000000 address range: 0xc00000 -- bus ID: 0 address type: prefetch address address base: 0xd0000000 address range: 0x2e000000 -- bus ID: 4 bus info: 0x01 parent bus ID: 0-- bus ID: 0 address modifier: add predefined range: 0x00000000-- bus ID: 0 address modifier: add predefined range: 0x00000001 ------------------------------------------------------------------------------- # SMP kernel config file options: # Required: options SMP # Symmetric MultiProcessor Kernel options APIC_IO # Symmetric (APIC) I/O # Useful: #options SMP_AUTOSTART # start the additional CPUs during boot # Optional (built-in defaults will work in most cases): #options NCPU=5 # number of CPUs #options NBUS=5 # number of busses #options NAPIC=1 # number of IO APICs #options NINTR=26 # number of INTs # Rogue hardware: # # Tyan Tomcat II: #options SMP_TIMER_NC # # # SuperMicro P6DNE: #options SMP_TIMER_NC # ===============================================================================