Author Topic: Building Qt5  (Read 27880 times)

OS4User

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Re: Building Qt5
« Reply #60 on: November 26, 2022, 02:34:25 pm »
Thanks for the link. They are taking a trick to check for OS support (checking for and catching (if necessary) an exception). Very instructive.

When CPUID executes with EAX set to 01H:

bit27  - OSXSAVE
A value of 1 indicates that the OS has set CR4.OSXSAVE[bit 18] to enable XSETBV/XGETBV instructions to access XCR0 and to support processor extended state management using XSAVE/XRSTOR. (https://www.felixcloutier.com/x86/cpuid)

May be that is a way  for  R3 application.

Lars

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Re: Building Qt5
« Reply #61 on: November 26, 2022, 05:24:15 pm »
You are right, that is the easiest and most straightforward way to detect OS support for AVX.
Unfortunately, there is nothing comparable to detect OS support for SSE (that is, CR4.OSFXSR being set instead of CR4.OSXSAVE being set). Looks like Intel never thinks any farther than up to the next corner.

Anyways. even for the later W4 kernels, OS support for SSE is in effect (I tried it and nothing crashed) and since we have 2022, that is sufficiently reliable information to build upon.

OS4User

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Re: Building Qt5
« Reply #62 on: November 26, 2022, 05:45:02 pm »
Anyways. even for the later W4 kernels, OS support for SSE is in effect (I tried it and nothing crashed) and since we have 2022, that is sufficiently reliable information to build upon.

Sure. You even can try to build AVX branch - since you have a good way to detect an OS support for it. ;)

Lars

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Re: Building Qt5
« Reply #63 on: November 27, 2022, 12:24:46 pm »
Anyways. even for the later W4 kernels, OS support for SSE is in effect (I tried it and nothing crashed) and since we have 2022, that is sufficiently reliable information to build upon.

Sure. You even can try to build AVX branch - since you have a good way to detect an OS support for it. ;)

Obviously, gcc supports automatic vectorization from C/C++ code but VAC and Watcom compilers do not. Since I never use gcc, I always have to hand code vectorization in assembler (which I do seldomly enough).
I don`t feel like handcoding a SSE version and a AVX version. The speedup with SSE for suitable core functions, compared to using general purpose registers, is already a factor of typically 16 (when using all 8 available XMM registers under 32-bit code) or even much higher, depending on data type (byte, word, dword, qword, single precision float, double precision float).
« Last Edit: November 27, 2022, 12:32:30 pm by Lars »