Daniela's Enhanced Drivers: Difference between revisions

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By [[Daniela Engert]]
By [[Daniela Engert]]


'''How to use this reference?'''


'''''How to use this reference?'''''
The information included on this web page is rather technical. For the non-technical users, we will explain how to use the system briefly:
# First, you need to identify the IDE chipset (or controller) used in your computer. This can be done via pci.exe or scanpci.exe utilities. For example, running pci.exe (by the command ''pci.exe'' from an OS/2 Command Prompt) on a system with an Intel-based motherboard* will show this record for the IDE controller amongst the output it generates. Locating the specific record for the controller is a task for the visitor. os2warp.be Support Services will not assist in this.
{| border="1" |- |Vendor 8086h Intel Corporation<br> Device 244Bh 82801BA UltraATA/100 IDE Controller (ICH2 B5 step)<br> Command 0005h (I/O Access, BusMaster)<br> Status 0280h (Supports Back-To-Back Trans., Medium Timing)<br> Revision 05h, Header Type 00h, Bus Latency 00h<br> Self test 00h (Self test not supported)<br> PCI Class Storage, type IDE<br> PCI EIDE Controller Features :<br> BusMaster EIDE is supported<br> Primary Channel is at I/O Port 01F0h and IRQ 14<br> Secondary Channel is at I/O Port 0170h and IRQ 15<br> Subsystem ID 24428086h 82801BA (ICH2) UltraDMA/100 IDE Controller (Guess Only!)<br> Subsystem Vendor 8086h Intel Corporation<br> Address 4 is an I/O Port : 0000F000h |}
From the first line, you can see that the controller's Vendor ID is 0x8086 (8086h), and the second line states the Device ID: 0x244B (244Bh). These hexadecimal numbers can respectively be considered the surname and the first name of your controller.


For more information about the pci.exe utility, os2warp.be Support Services hosts this article. The pci.exe utility can be downloaded via this web site via the Downloads Page.
The information included on this web page is rather technical. For the non-technical
users, we will explain how to use the system briefly:


<blockquote>
*: Note not all Intel motherboard have this chipset integrated on them.
# First, you need to identify the IDE chipset (or controller) used in your      computer. This can be done via pci.exe or scanpci.exe utilities. For example,      running pci.exe (by the command ''pci.exe'' from an OS/2 Command Prompt)      on a system with an Intel-based motherboard* will show this record for the      IDE controller amongst the output it generates. Locating the specific record      for the controller is a task for the visitor. os2warp.be Support Services      will not assist in this.          {| border="1" |- |<blockquote> Vendor 8086h Intel Corporation<br> Device 244Bh 82801BA UltraATA/100 IDE Controller (ICH2 B5 step)<br> Command 0005h (I/O Access, BusMaster)<br> Status 0280h (Supports Back-To-Back Trans., Medium Timing)<br> Revision 05h, Header Type 00h, Bus Latency 00h<br> Self test 00h (Self test not supported)<br> PCI Class Storage, type IDE<br> PCI EIDE Controller Features :<br> BusMaster EIDE is supported<br> Primary Channel is at I/O Port 01F0h and IRQ 14<br> Secondary Channel is at I/O Port 0170h and IRQ 15<br> Subsystem ID 24428086h 82801BA (ICH2) UltraDMA/100 IDE Controller (Guess Only!)<br> Subsystem Vendor 8086h Intel Corporation<br> Address 4 is an I/O Port : 0000F000h  </blockquote> |}  From the first line, you can see that the controller's      Vendor ID is 0x8086 (8086h), and the second line states the Device ID: 0x244B      (244Bh). These hexadecimal numbers can respectively be considered the surname      and the first name of your controller.<br>      For more information about the pci.exe utility, os2warp.be Support Services      hosts [[this article]]. The pci.exe      utility can be downloaded via this web site via the Downloads Page.<br>      *: Note not all Intel motherboard have this chipset integrated on them.
# Now you have to see in the tables below if this device is supported. This can be done by browsing on these Vendor and Device IDs. In each table, the first cell in the first row displays the manufacturer name, followed by a column and the Vendor ID. All rows below have the device name and correct Device ID in the first column.
# Now you have to see in the tables below if this device is supported. This       can be done by browsing on these Vendor and Device IDs. In each table, the       first cell in the first row displays the manufacturer name, followed by       a column and the Vendor ID. All rows below have the device name and correct       Device ID in the first column.
# Based on these IDs, a particular controller can be located on this page if it is officially supported by the Dani1S506 device driver. If the controller is not listed, this doesn't mean that it isn't supported, though. In that case, you'll just have to try it out, and if it works, you should report it so that we can either include official support for it and/or list it here.
# Based on these IDs, a particular controller can be located on this page       if it is officially supported by the Dani1S506 device driver. If the controller       is not listed, this doesn't mean that it isn't supported, though. In that       case, you'll just have to try it out, and if it works, you should report       it so that we can either include official support for it and/or list it       here.
# Sometimes there are several versions of a particular controller. In that case, the revision column will indicate the appropriate version (second column).
# Sometimes there are several versions of a particular controller. In that       case, the revision column will indicate the appropriate version (second       column).
# The remaining columns display hardware information, like the different speeds and IDE technologies which are supported by the controller/chipset. A legend what the symbols mean is included at the bottom of this page.
# The remaining columns display hardware information, like the different       speeds and IDE technologies which are supported by the controller/chipset.       A legend what the symbols mean is included at the bottom of this page.
</blockquote>             
{| border="1"
{| border="1"
|-
|-
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|-
|-
|0x0005 AEC 6210
|0x0005 AEC 6210
|  
|
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
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|-
|-
|0x0006 AEC 6260
|0x0006 AEC 6260
|  
|  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
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|-
|-
|0x0007 AEC 6260
|0x0007 AEC 6260
|  
|  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
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|-
|-
|0x0009 AEC 6280/6880
|0x0009 AEC 6280/6880
|  
|  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
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* 6210 (possible 6260) - task file registers are inaccessible until busmaster engine is stopped.
* 6210 (possible 6260) - task file registers are inaccessible until busmaster engine is stopped.
* possibly all - both channels share internal resources. Serialization is required.
* possibly all - both channels share internal resources. Serialization is required.
|}


|}<br>           
{| border="1"
{| border="1"
|-
|-
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|-
|-
|0x5229 M5229
|0x5229 M5229
|< 0x20  
|< 0x20  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
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|-
|-
|  
|  
|< 0xC1 1533, 1543E/F  
|< 0xC1 1533, 1543E/F  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
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|-
|-
|  
|  
|< 0xC2 1543C  
|< 0xC2 1543C  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
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|-
|-
|  
|  
|< 0xC3/0x12 1543C-E  
|< 0xC3/0x12 1543C-E  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
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|-
|-
|  
|  
|< 0xC4 1535, 1553, 1543C-B, 1535D  
|< 0xC4 1535, 1553, 1543C-B, 1535D  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
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|-
|-
|  
|  
|== 0xC4 1535D+  
|== 0xC4 1535D+  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
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|-
|-
|  
|  
|> 0xC4 1535D+  
|> 0xC4 1535D+  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 201: Line 201:
* 1543C-Bx - must stop busmaster reads with 0x00 instead of 0x08
* 1543C-Bx - must stop busmaster reads with 0x00 instead of 0x08
* >= 0xC5 - no host side cable type detection.
* >= 0xC5 - no host side cable type detection.
|}


|}<br>           
{| border="1"
{| border="1"
|-
|-
Line 219: Line 219:
|-
|-
|0x7401 AMD 751
|0x7401 AMD 751
|  
|  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 232: Line 232:
|-
|-
|0x7409 AMD 756
|0x7409 AMD 756
|  
|  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 245: Line 245:
|-
|-
|0x7411 AMD 766 MP
|0x7411 AMD 766 MP
|  
|  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 258: Line 258:
|-
|-
|0x7441 AMD 768 MPX
|0x7441 AMD 768 MPX
|  
|  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
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|-
|-
|0x7469 AMD 8111
|0x7469 AMD 8111
|  
|  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
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* 756 - SingleWord DMA doesn't work on early chip revisions.
* 756 - SingleWord DMA doesn't work on early chip revisions.
* 766 - read/write prefetches must be disabled to defeat infinite PCI bus retries.
* 766 - read/write prefetches must be disabled to defeat infinite PCI bus retries.
|}


|}<br>           
{| border="1"
{| border="1"
|-
|-
Line 306: Line 306:
|-
|-
|0x0640 CMD 640
|0x0640 CMD 640
|  
|  
|[[Image:nope.gif]]
|[[Image:nope.gif]]
|[[Image:nope.gif]]
|[[Image:nope.gif]]
Line 319: Line 319:
|-
|-
|0x0643 CMD 643
|0x0643 CMD 643
|< 03  
|< 03  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
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|[[Image:check.gif]]
|[[Image:check.gif]]
|-
|-
|  
|
|>= 03  
|>= 03  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
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|-
|-
|0x0646 CMD 646
|0x0646 CMD 646
|< 03  
|< 03  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
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|-
|-
|  
|  
|>= 03  
|>= 03  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 371: Line 371:
|-
|-
|0x0648 CMD 648
|0x0648 CMD 648
|  
|  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 384: Line 384:
|-
|-
|0x0649 CMD 649
|0x0649 CMD 649
|  
|  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 397: Line 397:
|-
|-
|0x0680 SiI 680
|0x0680 SiI 680
|  
|  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 410: Line 410:
|-
|-
|0x3112 SiI 3112
|0x3112 SiI 3112
|  
|  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 421: Line 421:
|[[Image:nope.gif]]
|[[Image:nope.gif]]
|[[Image:checkl.gif]]
|[[Image:checkl.gif]]
|}<br>           
|}
 
{| border="1"
{| border="1"
|-
|-
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|-
|-
|0x0102 CX5530
|0x0102 CX5530
|  
|  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
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* all - busmaster transfers need to be 16 byte aligned instead of word aligned.
* all - busmaster transfers need to be 16 byte aligned instead of word aligned.
* all - a DMA block of 64KiB comes out as 0 bytes in the DMA engine.
* all - a DMA block of 64KiB comes out as 0 bytes in the DMA engine.
|}


|}<br>           
{| border="1"
{| border="1"
|-
|-
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|-
|-
|0x0004 HPT 36x/37x
|0x0004 HPT 36x/37x
|<=01 HPT 366  
|<=01 HPT 366  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 485: Line 486:
|-
|-
|  
|  
|02 HPT 368  
|02 HPT 368  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 498: Line 499:
|-
|-
|  
|  
|03 HPT 370  
|03 HPT 370  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 511: Line 512:
|-
|-
|  
|  
|04 HPT 370A  
|04 HPT 370A  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 524: Line 525:
|-
|-
|  
|  
|05 HPT 372  
|05 HPT 372  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 537: Line 538:
|-
|-
|0x0005 HPT 372A
|0x0005 HPT 372A
|  
|  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
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|-
|-
|0x0006 HPT 302
|0x0006 HPT 302
|  
|  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 563: Line 564:
|-
|-
|0x0007 HPT 371
|0x0007 HPT 371
|  
|  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 576: Line 577:
|-
|-
|0x0008 HPT 36x/37x dual
|0x0008 HPT 36x/37x dual
|07  
|07  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 589: Line 590:
|-
|-
|0x0009 HPT 372N
|0x0009 HPT 372N
|  
|  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 606: Line 607:
* HPT366 - random PCI bus lockups in case of too long bursts.
* HPT366 - random PCI bus lockups in case of too long bursts.
* HPT366 - IBM DTLA series drives must be set to Ultra DMA mode 5 (!!) to work reliable at Ultra DMA mode 4 speed.
* HPT366 - IBM DTLA series drives must be set to Ultra DMA mode 5 (!!) to work reliable at Ultra DMA mode 4 speed.
|}


|}<br>           
{| border="1"
{| border="1"
|-
|-
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|-
|-
|0x1230 PIIX
|0x1230 PIIX
|  
|  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 637: Line 638:
|-
|-
|  
|  
|< 02  
|< 02  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:nope.gif]]
|[[Image:nope.gif]]
Line 650: Line 651:
|-
|-
|SbID: 0x84C4 OrionSbRev: < 04
|SbID: 0x84C4 OrionSbRev: < 04
|< 02  
|< 02  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:nope.gif]]
|[[Image:nope.gif]]
Line 663: Line 664:
|-
|-
|0x7010 PIIX3
|0x7010 PIIX3
|  
|  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 676: Line 677:
|-
|-
|0x7111 PIIX4
|0x7111 PIIX4
|  
|  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 689: Line 690:
|-
|-
|0x7199 PIIX4 MX
|0x7199 PIIX4 MX
|  
|  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 702: Line 703:
|-
|-
|0x2411 ICH
|0x2411 ICH
|  
|  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 715: Line 716:
|-
|-
|0x7601 ICH
|0x7601 ICH
|  
|  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 728: Line 729:
|-
|-
|0x2421 ICH0
|0x2421 ICH0
|  
|  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 741: Line 742:
|-
|-
|0x244B ICH2
|0x244B ICH2
|  
|  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 754: Line 755:
|-
|-
|0x244A ICH2 mobile
|0x244A ICH2 mobile
|  
|  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 767: Line 768:
|-
|-
|0x245B C-ICH
|0x245B C-ICH
|  
|  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 780: Line 781:
|-
|-
|0x248B ICH3
|0x248B ICH3
|  
|  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 793: Line 794:
|-
|-
|0x248A ICH3 mobile
|0x248A ICH3 mobile
|  
|  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 806: Line 807:
|-
|-
|0x24CB ICH4
|0x24CB ICH4
|  
|  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 819: Line 820:
|-
|-
|0x24CA ICH4 mobile
|0x24CA ICH4 mobile
|  
|  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 832: Line 833:
|-
|-
|0x24DB ICH5 (PATA)
|0x24DB ICH5 (PATA)
|  
|  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 845: Line 846:
|-
|-
|0x24D1 ICH5 (SATA)
|0x24D1 ICH5 (SATA)
|  
|  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 858: Line 859:
|-
|-
|0x24DF ICH5R (SATA)
|0x24DF ICH5R (SATA)
|  
|  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 874: Line 875:
* PIIX3 - Some chips 'forget' to assert the IRQ sometimes. These chips are not detectable in advance.
* PIIX3 - Some chips 'forget' to assert the IRQ sometimes. These chips are not detectable in advance.
* ICH2+ - Despite the docs, the ATA/100 capable chips also can do ATA/133
* ICH2+ - Despite the docs, the ATA/100 capable chips also can do ATA/133
|-
|-
|Notes:
|Notes:
|SbID = Southbridge or Host ID<br>
|SbID = Southbridge or Host ID<br>
SbRev = Southbridge or Host Revision
SbRev = Southbridge or Host Revision
|}<br>           
|}
 
{| border="1"
{| border="1"
|-
|-
Line 896: Line 897:
|-
|-
|0x052 SCx200
|0x052 SCx200
|  
|  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 907: Line 908:
|[[Image:nope.gif]]
|[[Image:nope.gif]]
|[[Image:nope.gif]]
|[[Image:nope.gif]]
|}<br>           
|}
 
{| border="1"
{| border="1"
|-
|-
Line 924: Line 926:
|-
|-
|0x01BC nForce
|0x01BC nForce
|  
|  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 937: Line 939:
|-
|-
|0x0065 nForce2
|0x0065 nForce2
|  
|  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 953: Line 955:
* all - no host side cable detection.
* all - no host side cable detection.
* all - read/write prefetches must be disabled to defeat infinite PCI bus retries.
* all - read/write prefetches must be disabled to defeat infinite PCI bus retries.
|}


|}<br>           
{| border="1"
{| border="1"
|-
|-
Line 971: Line 973:
|-
|-
|0xC621 n/a
|0xC621 n/a
|  
|  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:nope.gif]]
|[[Image:nope.gif]]
Line 984: Line 986:
|-
|-
|0xC558 Viper
|0xC558 Viper
|  
|  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 997: Line 999:
|-
|-
|0xD568
|0xD568
|< 0xC700 Viper  
|< 0xC700 Viper  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 1,010: Line 1,012:
|-
|-
|  
|  
|>= 0xC700 FireStar/Vendetta?  
|>= 0xC700 FireStar/Vendetta?  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 1,023: Line 1,025:
|-
|-
|0xD721 Vendetta
|0xD721 Vendetta
|  
|  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 1,036: Line 1,038:
|-
|-
|0xD768 Vendetta
|0xD768 Vendetta
|  
|  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 1,052: Line 1,054:
* C621 - both channels share internal resources. Serialization is required.
* C621 - both channels share internal resources. Serialization is required.
* FireStar - Ultra DMA works reliably only at mode 0. Update: not even that! Better do MWDMA2 at most.
* FireStar - Ultra DMA works reliably only at mode 0. Update: not even that! Better do MWDMA2 at most.
|}


|}<br>           
{| border="1"
{| border="1"
|-
|-
Line 1,070: Line 1,072:
|-
|-
|0x4D33 PDC20246 Ultra33
|0x4D33 PDC20246 Ultra33
|  
|  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 1,083: Line 1,085:
|-
|-
|0x4D38 PDC20262 Ultra66
|0x4D38 PDC20262 Ultra66
|  
|  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 1,096: Line 1,098:
|-
|-
|0x0D38 PDC20263 Ultra66
|0x0D38 PDC20263 Ultra66
|  
|  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 1,109: Line 1,111:
|-
|-
|0x0D30 PDC20265 Ultra100
|0x0D30 PDC20265 Ultra100
|  
|  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 1,122: Line 1,124:
|-
|-
|0x4D30 PDC20267 Ultra100
|0x4D30 PDC20267 Ultra100
|  
|  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 1,135: Line 1,137:
|-
|-
|0x4D68 PDC20268 Ultra100 TX2
|0x4D68 PDC20268 Ultra100 TX2
|  
|  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 1,148: Line 1,150:
|-
|-
|0x6268 PDC20270 Ultra100 TX2
|0x6268 PDC20270 Ultra100 TX2
|  
|  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 1,161: Line 1,163:
|-
|-
|0x4D69 PDC20269 Ultra133 TX2
|0x4D69 PDC20269 Ultra133 TX2
|  
|  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 1,174: Line 1,176:
|-
|-
|0x6269 PDC20271 Ultra133 TX2
|0x6269 PDC20271 Ultra133 TX2
|  
|  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 1,187: Line 1,189:
|-
|-
|0x1275 PDC20275 Ultra133 TX2
|0x1275 PDC20275 Ultra133 TX2
|  
|  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 1,200: Line 1,202:
|-
|-
|0x5275 PDC20276 Ultra133 TX2
|0x5275 PDC20276 Ultra133 TX2
|  
|  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 1,213: Line 1,215:
|-
|-
|0x7275 PDC20277 Ultra133 TX2
|0x7275 PDC20277 Ultra133 TX2
|  
|  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 1,231: Line 1,233:
* Ultra66/100 - "a LBA48 DMA mode transfer needs an extra ""kick""."
* Ultra66/100 - "a LBA48 DMA mode transfer needs an extra ""kick""."
* Ultra66/100 - "ATAPI DMA should work according to Windows drivers, but the register model is very ""strange""."
* Ultra66/100 - "ATAPI DMA should work according to Windows drivers, but the register model is very ""strange""."
|}


|}<br>           
{| border="1"
{| border="1"
|-
|-
Line 1,249: Line 1,251:
|-
|-
|0x0211 OSB4
|0x0211 OSB4
|  
|  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 1,262: Line 1,264:
|-
|-
|0x0212 CSB5
|0x0212 CSB5
|< 0x92  
|< 0x92  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 1,275: Line 1,277:
|-
|-
|  
|  
|>= 0x92  
|>= 0x92  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 1,288: Line 1,290:
|-
|-
|0x0213 CSB6
|0x0213 CSB6
|< 0xA0  
|< 0xA0  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 1,301: Line 1,303:
|-
|-
|  
|  
|>= 0xA0  
|>= 0xA0  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 1,321: Line 1,323:
* CSB5 - no host side cable type detection (vendor specific).
* CSB5 - no host side cable type detection (vendor specific).
* CSB6 - no host side cable type detection (vendor specific).
* CSB6 - no host side cable type detection (vendor specific).
|}


|}<br>           
{| border="1"
{| border="1"
|-
|-
Line 1,339: Line 1,341:
|-
|-
|0x5513 5513
|0x5513 5513
|< 0xD0  
|< 0xD0  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 1,352: Line 1,354:
|-
|-
|  
|  
|>= 0xD0  
|>= 0xD0  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 1,365: Line 1,367:
|-
|-
|SbID: >= 0x530
|SbID: >= 0x530
|>= 0xD0  
|>= 0xD0  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 1,378: Line 1,380:
|-
|-
|SbID: == 0x0630
|SbID: == 0x0630
|>= 0xD0  
|>= 0xD0  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 1,391: Line 1,393:
|-
|-
|SbID: == 0x0630SbRev: >= 0x30
|SbID: == 0x0630SbRev: >= 0x30
|>= 0xD0  
|>= 0xD0  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 1,404: Line 1,406:
|-
|-
|SbID: > 0x0630
|SbID: > 0x0630
|>= 0xD0  
|>= 0xD0  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 1,417: Line 1,419:
|-
|-
|SbID: 0x0961SbRev: < 0x10
|SbID: 0x0961SbRev: < 0x10
|>= 0xD0  
|>= 0xD0  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 1,430: Line 1,432:
|-
|-
|SbID: 0x0961SbRev: >= 0x10
|SbID: 0x0961SbRev: >= 0x10
|>= 0xD0  
|>= 0xD0  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 1,443: Line 1,445:
|-
|-
|SbID: >= 0x0961
|SbID: >= 0x0961
|>= 0xD0  
|>= 0xD0  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 1,456: Line 1,458:
|-
|-
|0x5517 5517
|0x5517 5517
|< 0x10  
|< 0x10  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 1,469: Line 1,471:
|-
|-
|  
|  
|>= 0x10  
|>= 0x10  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 1,482: Line 1,484:
|-
|-
|0x5518 5518
|0x5518 5518
|  
|  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 1,497: Line 1,499:
|
|
* older Sis - don't touch the busmaster registers too early after interrupt
* older Sis - don't touch the busmaster registers too early after interrupt
|-
|-
|Notes:
|Notes:
|SbID = Southbridge or Host ID<br>
|SbID = Southbridge or Host ID<br>
SbRev = Southbridge or Host Revision
SbRev = Southbridge or Host Revision
|}<br>           
|}
 
{| border="1"
{| border="1"
|-
|-
Line 1,519: Line 1,521:
|-
|-
|0x9130 SLC90E66
|0x9130 SLC90E66
|  
|  
|[[Image:vraag.gif]]
|[[Image:vraag.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 1,530: Line 1,532:
|[[Image:nope.gif]]
|[[Image:nope.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|}<br>           
|}
 
{| border="1"
{| border="1"
|-
|-
Line 1,547: Line 1,550:
|-
|-
|0x1571 571
|0x1571 571
|  
|  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 1,561: Line 1,564:
|0x0571 571<br>
|0x0571 571<br>
SbID: 0x0586
SbID: 0x0586
|  
|  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 1,574: Line 1,577:
|-
|-
|SbID: 0x0586SbRev: >= 0x20 586A/B
|SbID: 0x0586SbRev: >= 0x20 586A/B
|  
|  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 1,587: Line 1,590:
|-
|-
|SbID: 0x0596SbRev: < 0x10 596/A
|SbID: 0x0596SbRev: < 0x10 596/A
|  
|  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 1,600: Line 1,603:
|-
|-
|SbID: 0x0596SbRev: >= 0x10 596B
|SbID: 0x0596SbRev: >= 0x10 596B
|  
|  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 1,613: Line 1,616:
|-
|-
|SbID: 0x0686SbRev: < 0x10 686
|SbID: 0x0686SbRev: < 0x10 686
|  
|  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 1,626: Line 1,629:
|-
|-
|SbID: 0x0686SbRev: < 0x40 686A
|SbID: 0x0686SbRev: < 0x40 686A
|  
|  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 1,639: Line 1,642:
|-
|-
|SbID: 0x0686SbRev: >= 0x40
|SbID: 0x0686SbRev: >= 0x40
|  
|  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 1,652: Line 1,655:
|-
|-
|SbID: 0x8231SbRev: VT8231
|SbID: 0x8231SbRev: VT8231
|  
|  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 1,665: Line 1,668:
|-
|-
|SbID: 0x3074SbRev: VT8233
|SbID: 0x3074SbRev: VT8233
|  
|  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 1,678: Line 1,681:
|-
|-
|SbID: 0x3109SbRev: VT8233c
|SbID: 0x3109SbRev: VT8233c
|  
|  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 1,691: Line 1,694:
|-
|-
|SbID: 0x3147SbRev: VT8233a
|SbID: 0x3147SbRev: VT8233a
|  
|  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 1,704: Line 1,707:
|-
|-
|SbID: 0x3177SbRev: VT8235
|SbID: 0x3177SbRev: VT8235
|  
|  
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
|[[Image:check.gif]]
Line 1,728: Line 1,731:
|SbID = Southbridge or Host ID<br>
|SbID = Southbridge or Host ID<br>
SbRev = Southbridge or Host Revision
SbRev = Southbridge or Host Revision
|}<br>
|}
Documentation status:<br>
 
<br> [[Image:nope.gif]] means "documentation not available"<br> [[Image:check.gif]] means "documentation publicly available"<br> [[Image:conf.gif]] means "documentation available, but confidential"<br> [[Image:checkl.gif]] or [[Image:confl.gif]] means "documentation partially available" or
Documentation status:
"other documentation applies here as well"<br>
 
[[Image:nope.gif]] means "documentation not available"
 
[[Image:check.gif]] means "documentation publicly available"
 
[[Image:conf.gif]] means "documentation available, but confidential"
 
[[Image:checkl.gif]] or [[Image:confl.gif]] means "documentation partially available" or "other documentation applies here as well"
 
Other status:


[[Image:att.gif]] or [[Image:checkl.gif]] means "requires special attention described in comments"
Other status: <br>
<br> [[Image:att.gif]] or [[Image:checkl.gif]] means "requires special attention described in comments"<br>


[[Category:Hardware]]
[[Category:Hardware]]

Revision as of 18:11, 12 May 2017

By Daniela Engert

How to use this reference?

The information included on this web page is rather technical. For the non-technical users, we will explain how to use the system briefly:

  1. First, you need to identify the IDE chipset (or controller) used in your computer. This can be done via pci.exe or scanpci.exe utilities. For example, running pci.exe (by the command pci.exe from an OS/2 Command Prompt) on a system with an Intel-based motherboard* will show this record for the IDE controller amongst the output it generates. Locating the specific record for the controller is a task for the visitor. os2warp.be Support Services will not assist in this.
From the first line, you can see that the controller's Vendor ID is 0x8086 (8086h), and the second line states the Device ID: 0x244B (244Bh). These hexadecimal numbers can respectively be considered the surname and the first name of your controller. For more information about the pci.exe utility, os2warp.be Support Services hosts this article. The pci.exe utility can be downloaded via this web site via the Downloads Page.
  • Note not all Intel motherboard have this chipset integrated on them.
  1. Now you have to see in the tables below if this device is supported. This can be done by browsing on these Vendor and Device IDs. In each table, the first cell in the first row displays the manufacturer name, followed by a column and the Vendor ID. All rows below have the device name and correct Device ID in the first column.
  2. Based on these IDs, a particular controller can be located on this page if it is officially supported by the Dani1S506 device driver. If the controller is not listed, this doesn't mean that it isn't supported, though. In that case, you'll just have to try it out, and if it works, you should report it so that we can either include official support for it and/or list it here.
  3. Sometimes there are several versions of a particular controller. In that case, the revision column will indicate the appropriate version (second column).
  4. The remaining columns display hardware information, like the different speeds and IDE technologies which are supported by the controller/chipset. A legend what the symbols mean is included at the bottom of this page.
AEC/Artop: 0x1191 Rev. ATA PIO 32bit ATA DMA LBA48 DMA ATAPI PIO 32bit ATAPI DMA ATA33 ATA66 ATA100 ATA133 Docs. avail.
0x0005 AEC 6210
0x0006 AEC 6260
0x0007 AEC 6260
0x0009 AEC 6280/6880
Comments
  • 6210 (possible 6260) - task file registers are inaccessible until busmaster engine is stopped.
  • possibly all - both channels share internal resources. Serialization is required.
Ali: 0x10B9 Rev. ATA PIO 32bit ATA DMA LBA48 DMA ATAPI PIO 32bit ATAPI DMA ATA33 ATA66 ATA100 ATA133 Docs. avail.
0x5229 M5229 < 0x20
< 0xC1 1533, 1543E/F
< 0xC2 1543C
< 0xC3/0x12 1543C-E
< 0xC4 1535, 1553, 1543C-B, 1535D
== 0xC4 1535D+
> 0xC4 1535D+
Comments
  • 1535 and better - busmaster engine 'active' status bit is nonfunctional in UltraDMA modes.
  • up to 1543C - can't do ATAPI DMA writes.
  • 1543C-E - UltraDMA CRC checker fails with older WDC disks.
  • 1543C-Bx - must stop busmaster reads with 0x00 instead of 0x08
  • >= 0xC5 - no host side cable type detection.
AMD: 0x1022 Rev. ATA PIO 32bit ATA DMA LBA48 DMA ATAPI PIO 32bit ATAPI DMA ATA33 ATA66 ATA100 ATA133 Docs. avail.
0x7401 AMD 751
0x7409 AMD 756
0x7411 AMD 766 MP
0x7441 AMD 768 MPX
0x7469 AMD 8111
Comments
  • 756 - no host side cable type detection.
  • 756 - SingleWord DMA doesn't work on early chip revisions.
  • 766 - read/write prefetches must be disabled to defeat infinite PCI bus retries.
CMD/Silicon Image: 0x1095 Rev. ATA PIO 32bit ATA DMA LBA48 DMA ATAPI PIO 32bit ATAPI DMA ATA33 ATA66 ATA100 ATA133 Docs. avail.
0x0640 CMD 640
0x0643 CMD 643 < 03
>= 03
0x0646 CMD 646 < 03
>= 03
0x0648 CMD 648
0x0649 CMD 649
0x0680 SiI 680
0x3112 SiI 3112 SATA SATA SATA
Cyrix: 0x1078 Rev. ATA PIO 32bit ATA DMA LBA48 DMA ATAPI PIO 32bit ATAPI DMA ATA33 ATA66 ATA100 ATA133 Docs. avail.
0x0102 CX5530
Comments
  • all - busmaster transfers need to be 16 byte aligned instead of word aligned.
  • all - a DMA block of 64KiB comes out as 0 bytes in the DMA engine.
HighPoint: 0x1103 Rev. ATA PIO 32bit ATA DMA LBA48 DMA ATAPI PIO 32bit ATAPI DMA ATA33 ATA66 ATA100 ATA133 Docs. avail.
0x0004 HPT 36x/37x <=01 HPT 366
02 HPT 368
03 HPT 370
04 HPT 370A
05 HPT 372
0x0005 HPT 372A
0x0006 HPT 302
0x0007 HPT 371
0x0008 HPT 36x/37x dual 07
0x0009 HPT 372N
Comments
  • HPT366 - random failures with several disks.
  • HPT366 - random PCI bus lockups in case of too long bursts.
  • HPT366 - IBM DTLA series drives must be set to Ultra DMA mode 5 (!!) to work reliable at Ultra DMA mode 4 speed.
Intel: 0x8086 Rev. ATA PIO 32bit ATA DMA LBA48 DMA ATAPI PIO 32bit ATAPI DMA ATA33 ATA66 ATA100 ATA133 Docs. avail.
0x1230 PIIX
< 02
SbID: 0x84C4 OrionSbRev: < 04 < 02
0x7010 PIIX3
0x7111 PIIX4
0x7199 PIIX4 MX
0x2411 ICH
0x7601 ICH
0x2421 ICH0
0x244B ICH2
0x244A ICH2 mobile
0x245B C-ICH
0x248B ICH3
0x248A ICH3 mobile
0x24CB ICH4
0x24CA ICH4 mobile
0x24DB ICH5 (PATA)
0x24D1 ICH5 (SATA) SATA SATA SATA
0x24DF ICH5R (SATA) SATA SATA SATA
Comments
  • PIIX3 - Some chips 'forget' to assert the IRQ sometimes. These chips are not detectable in advance.
  • ICH2+ - Despite the docs, the ATA/100 capable chips also can do ATA/133
Notes: SbID = Southbridge or Host ID

SbRev = Southbridge or Host Revision

Nation Semiconductor: 0x100B Rev. ATA PIO 32bit ATA DMA LBA48 DMA ATAPI PIO 32bit ATAPI DMA ATA33 ATA66 ATA100 ATA133 Docs. avail.
0x052 SCx200
Nvidia: 0x10DE Rev. ATA PIO 32bit ATA DMA LBA48 DMA ATAPI PIO 32bit ATAPI DMA ATA33 ATA66 ATA100 ATA133 Docs. avail.
0x01BC nForce
0x0065 nForce2
Comments
  • all - no host side cable detection.
  • all - read/write prefetches must be disabled to defeat infinite PCI bus retries.
Opti: 0x1045 Rev. ATA PIO 32bit ATA DMA LBA48 DMA ATAPI PIO 32bit ATAPI DMA ATA33 ATA66 ATA100 ATA133 Docs. avail.
0xC621 n/a
0xC558 Viper
0xD568 < 0xC700 Viper
>= 0xC700 FireStar/Vendetta?
0xD721 Vendetta
0xD768 Vendetta
Comments
  • C621 - both channels share internal resources. Serialization is required.
  • FireStar - Ultra DMA works reliably only at mode 0. Update: not even that! Better do MWDMA2 at most.
Promise: 0x105A Rev. ATA PIO 32bit ATA DMA LBA48 DMA ATAPI PIO 32bit ATAPI DMA ATA33 ATA66 ATA100 ATA133 Docs. avail.
0x4D33 PDC20246 Ultra33
0x4D38 PDC20262 Ultra66
0x0D38 PDC20263 Ultra66
0x0D30 PDC20265 Ultra100
0x4D30 PDC20267 Ultra100
0x4D68 PDC20268 Ultra100 TX2
0x6268 PDC20270 Ultra100 TX2
0x4D69 PDC20269 Ultra133 TX2
0x6269 PDC20271 Ultra133 TX2
0x1275 PDC20275 Ultra133 TX2
0x5275 PDC20276 Ultra133 TX2
0x7275 PDC20277 Ultra133 TX2
Comments
  • up to Ultra100 - don't issue superfluous PIO transfer mode setups.
  • up to Ultra100 - if any device is initialized to UltraDMA, you need to reset the channel if you want to select MultiWord DMA instead.
  • Ultra66/100 - "a LBA48 DMA mode transfer needs an extra ""kick""."
  • Ultra66/100 - "ATAPI DMA should work according to Windows drivers, but the register model is very ""strange""."
ServerWorks: 0x1166 Rev. ATA PIO 32bit ATA DMA LBA48 DMA ATAPI PIO 32bit ATAPI DMA ATA33 ATA66 ATA100 ATA133 Docs. avail.
0x0211 OSB4
0x0212 CSB5 < 0x92
>= 0x92
0x0213 CSB6 < 0xA0
>= 0xA0
Comments
  • OSB4 - at least early revisions lock up on ATAPI DMA aborts
  • OSB4 - at least some chip revisions can't do Ultra DMA mode 1 and above.
  • OSB4 - some chip revisions may get stuck in the DMA engine in Ultra DMA with some disks.
  • CSB5 - trickles up to 3 (instead of common 2) words on UDMA throttle in ATA/100 mode. This may cause FIFO overruns in the units. Seen on Seagate Barracuda IV.
  • CSB5 - no host side cable type detection (vendor specific).
  • CSB6 - no host side cable type detection (vendor specific).
Sis: 0x1039 Rev. ATA PIO 32bit ATA DMA LBA48 DMA ATAPI PIO 32bit ATAPI DMA ATA33 ATA66 ATA100 ATA133 Docs. avail.
0x5513 5513 < 0xD0
>= 0xD0
SbID: >= 0x530 >= 0xD0
SbID: == 0x0630 >= 0xD0
SbID: == 0x0630SbRev: >= 0x30 >= 0xD0
SbID: > 0x0630 >= 0xD0
SbID: 0x0961SbRev: < 0x10 >= 0xD0
SbID: 0x0961SbRev: >= 0x10 >= 0xD0
SbID: >= 0x0961 >= 0xD0
0x5517 5517 < 0x10
>= 0x10
0x5518 5518
Comments
  • older Sis - don't touch the busmaster registers too early after interrupt
Notes: SbID = Southbridge or Host ID

SbRev = Southbridge or Host Revision

SMSC: 0x1055 Rev. ATA PIO 32bit ATA DMA LBA48 DMA ATAPI PIO 32bit ATAPI DMA ATA33 ATA66 ATA100 ATA133 Docs. avail.
0x9130 SLC90E66
Via: 0x1106 Rev. ATA PIO 32bit ATA DMA LBA48 DMA ATAPI PIO 32bit ATAPI DMA ATA33 ATA66 ATA100 ATA133 Docs. avail.
0x1571 571
0x0571 571

SbID: 0x0586

SbID: 0x0586SbRev: >= 0x20 586A/B
SbID: 0x0596SbRev: < 0x10 596/A
SbID: 0x0596SbRev: >= 0x10 596B
SbID: 0x0686SbRev: < 0x10 686
SbID: 0x0686SbRev: < 0x40 686A
SbID: 0x0686SbRev: >= 0x40
SbID: 0x8231SbRev: VT8231
SbID: 0x3074SbRev: VT8233
SbID: 0x3109SbRev: VT8233c
SbID: 0x3147SbRev: VT8233a
SbID: 0x3177SbRev: VT8235
Comments
  • all - no host side cable type detection.
  • all - the busmaster 'active' bit doesn't match the actual busmaster state.
  • 596B - don't touch the busmaster registers too early after interrupt
  • 596B - don't touch the taskfile registers before stopping the busmaster!
  • 686 - rev 40/41 and VT8231 rev 10/11 have the PCI corruption bug!
Notes: SbID = Southbridge or Host ID

SbRev = Southbridge or Host Revision

Documentation status:

means "documentation not available"

means "documentation publicly available"

means "documentation available, but confidential"

or means "documentation partially available" or "other documentation applies here as well"

Other status:

or means "requires special attention described in comments"